Circuit optimization using device layout motifs

As technology reaches atomic scales, circuit performance is significantly affected by the variability of electrical properties within transistors such as random dopant fluctuation (RDF), line edge roughness (LER), and layout driven variations. This increases pressure on designers to find methodologies that more effectively mitigate the impact of device parameter fluctuations and improve circuit performance. In this paper, a novel alternative layout style of devices is proposed: an O-shaped device layout motif. A 3D O-shaped device simulation including LER variability source is performed using TCAD simulation in order to investigate and exploit the variability characteristics of O-shaped devices at both device level and circuit level. The corresponding statistical variability models enabling efficient circuit-level simulations using SPICE are extracted from TCAD simulation results. In order to further explore this novel device layout motif's impact on circuit design, a number of logic gates are used as candidates which are constructed using this novel device. The experimental results show that the worse case delay of logic gates can be reduced through mixed combinations of O-shaped devices and regular devices. At the same time, effects of variability on propagation delay can be mitigated.