On the performance of SC-MMSE-FD equalization for fixed-point implementations

A fixed-point implementation of a minimum mean square error (MMSE) based frequency domain (FD) equalizer with soft interference cancellation (SC) is studied. The equalizer additionally processes a priori information about the transmitted symbols and is used for turbo equalization. In this paper, we analyze the quantization and the clipping for different fixed-point representations and modulation schemes. The analysis allows to derive efficient representations for all symbols within the equalizer. This procedure is demonstrated for a generic system configuration featuring a 16-QAM. Finally, a fixed-point implementation in an integrated design environment for FPGAs verifies the theoretical studies and shows the device utilizations for different FPGAs that are embedded in current software defined radios. The results show, that on average 10 bits per symbol are required for a near-optimum equalization performance utilizing less than 8% area of state of the art FPGAs.