Programmable Low-Power Multicore Coprocessor Architecture for HEVC/H.265 In-Loop Filtering

The High Efficiency Video Coding (HEVC) in-loop filtering is designed to reduce coding artifacts caused by image transforms and quantizations. HEVC in-loop filtering is divided to the deblocking filter and the sample adaptive offset filter, and these two filters take about 20% of total decoding time. This paper presents a very low-power (39 mW) programmable coprocessor architecture to HEVC in-loop filtering, targeting especially embedded devices. The solution consists of three identical tiny application specific instruction set processor cores that are able to process 30 Full-HD intra-luma frames/s when the operating frequency is 350 MHz. The cores are fully programmable by C-language, which allows easy software modifications and updates. Although the cores have been designed for in-loop filtering, they are also capable of signal processing tasks that demand high performance. In terms of energy efficiency, the proposed architecture falls clearly between application-specified integrated circuits and conventional embedded processors, and thus forms a new-generation solution for HEVC in-loop filtering.