Characterization of the voltage and electric field stresses in multi-cell solid-state transformers

Solid-State Transformers (SSTs) are a promising technology since they enable a reduction in weight and volume of transformers while integrating new functionalities and services in the grid. However, a new kind of electric stress for the insulation occurs in this type of power converter, given that low-frequency medium-voltage stresses are mixed with high-frequency stresses generated by the converter's switching actions. This paper analyzes, in time and frequency domains, the voltage stresses appearing in cascaded converters, employing converter cells based on two-level or three-level bridge legs. The highest electric fields occur in the medium-frequency transformers of the converter cells' DC-DC converters, which provide galvanic isolation within the SST. Numerical simulations of the electric field distributions in these transformers are presented for the different frequency components and the impact of the converter topology on the insulation stress is highlighted. Furthermore, it is shown that the dielectric losses of the transformer can be neglected despite the presence of high-frequency harmonics. Finally, a transformer insulation concept based on semiconducting tape is proposed.