Realization of receiver architectures using VLSI DSP techniques for broadcast channel in LTE

Long Term Evolution (LTE) of UMTS Terrestrial Radio Access and Radio Access Network is a Fourth Generation wireless broadband technology which is capable of providing backward compatibility with 2G (Second Generation) and 3G (Third Generation) technologies. LTE is able to deliver high data rate and low latency with reduced cost. It uses the frame structure as Time Division Duplexing (TDD) Land Frequency Division Duplexing (FDD). The broadcast channel in LTE is Physical Broadcast Channel (PBCH) information is divided into two categories one is Master Information Block (MIB) consists of a limited number of the most frequently transmitted parameters essential for initial access to the cell, and is carried on the PBCH and the other System Information Blocks (SIB) at the physical layer are multiplexed together with unicast data transmitted. The main objective of this paper is the realization of receiver architectures for PBCH in LTE considering Single Input Single Output (SISO), Multiple Input Single Output (MISO), Single Input Multi Output (SIMO), and Multiple Input Multiple Output (MIMO). The Receiver processing steps involves as channel de-estimation, demodulation, minimum mean square error (MMSE) and among the received data minimum value is calculated using the comparator at receiver side. By applying the following VLSI DSP methods folding to reduce the number of resource elements required and another method consider to reduce the delay is Super scalar processing method and the results are compared between the direct method, folding method and super scalar method. Based on simulation and implementation, results are discussed in terms of Register Transfer Level (RTL) design, Field Programmable Gate Arrays (FPGA) editor, power estimation and resource estimation. To simulate all the modules of all PBCH channel Verilog code, Modelsim is used. For synthesis and implementation of the above architecture PlanAhead 13.4 tool on Virtex-5, xc5vlx50tff1136-1 device board is used.