Hardware realizable lattice-reduction-aided detectors for large-scale MIMO systems

Because of their lower complexity and better error performance over K-best detectors, lattice-reduction (LR)-aided K-best detectors have recently proposed for large-scale multiinput multi-output (MIMO) detection. Among existing LR-aided K-best detectors, complex LR-aided K-best detector is more attractive compared to its real counterpart due to its potential lower latency and resources. However, one main difficulty in hardware implementation of complex LR-aided K-best is to efficiently find top K children of each layer in complex domain. In this paper, we propose and implement an LR-aided K-best algorithm that efficiently finds top K children in each layer when K is relatively small. Our implementation results on Xilinx VC707 FPGA board show that, with the aid of LR, the proposed LR-aided K-best implementation can support 3 Gbps transmissions for 16×16 MIMO systems with 1024-QAM with about 2.7 dB loss to the maximum likelihood detector at bit-error rate 10
^-4
.