A 0.0045- $\hbox{mm}^{2}$ 32.4- $\mu\hbox{W} $ Two-Stage Amplifier for pF-to-nF Load Using CM Frequency Compensation

This brief reports an embedded capacitor multiplier (CM) frequency compensation technique to realize an extremely compact micropower two-stage amplifier for wide capacitive load (C
_L
) drivability. It features: 1) a valuable left half-plane zero to enhance the closed-loop stability over a wide range of C
_L
; 2) no extra bias circuit and power, as the CM is embedded into the first stage of the amplifier, and 3) only one very small (subpicofarad) compensation capacitor improving the transient settling and area efficiency. Detailed analytical treatments of the amplifier offer the critical insights for device sizing and optimization. Fabricated in 0.18-μm CMOS, the amplifier measures 3.06-MHz unity-gain frequency (UGF), 1.76-V/μs average slew rate (SR), and 74° phase margin (PM) at 20-pF C
_L
, and 0.22-MHz UGF, 0.049-V/μs SR, and 59.8° PM at 15-nF C
_L
. The die size is 0.0045 mm
²
, and power is 32.4 μW at 1.2 V. Competitive large- and small-signal figures of merit are achieved with respect to the state of the art.