A 1.3 V low-power 430 MHz front-end using a standard digital CMOS process [ISM wireless link]

A low-power and low-voltage (LP/LV) RF front-end operating at 430 MHz and implemented in a standard 0.5 /spl mu/m digital CMOS process is described. Specific LP/LV bias techniques and design tradeoffs are discussed and their application to the design of a fully integrated direct-conversion receiver is presented. The RF building blocks including a 200 /spl mu/A LNA, two different 50 /spl mu/A mixers and a ring-oscillator with differential I-Q outputs consuming 300 /spl mu/A at 430 MHz, have been manufactured and their performances measured. Taking into account the severe power budget, a total double sideband (DSB) noise figure of 17 dB was achieved, together with a spurious free dynamic range of 55 dB at 60 kHz bandwidth, which is sufficient for the targeted application.