A low-power 16-bit multiplier-accumulator using series-regulated mixed swing techniques

This paper describes an on-chip series-regulated mixed swing methodology with sleep-mode control for lowering the power consumption of high-performance DSP multiplier-accumulator (MAC) circuits. A 16*16+36-bit overlapped bit-pair Booth recoded Wallace tree MAC is fabricated in a commercial 0.5 /spl mu/m CMOS process in the proposed series-regulated methodology and conventional static CMOS. Up to 2.55/spl times/ reduction in energy/operation is measured over static CMOS, while offering a simultaneous 1.8/spl times/ improvement in low-voltage manufacturability. At the maximum clock frequency of 67 MHz, the proposed approach consumes a total MAC power of 16.6 mW in active mode and 152.5 nW in standby mode. Measured peak-peak power/ground bounce is under 8% of the regulated low-swing voltage. Experimental results from comparisons in three additional (0.35 /spl mu/m, 0.25 /spl mu/m, 0.16 /spl mu/m) CMOS and fully-depleted SOI processes are also presented to demonstrate improved savings over static CMOS with process scaling.