Re-inventing the DRAM for embedded use: a compiled, wide-databus DRAM macrocell with high bandwidth and low power

This paper describes a compiled DRAM macro with a novel data bus architecture in which ultra-wide buses do not cost silicon area. Moreover, the architecture consumes less power for a given data transfer rate or offers much higher data rates for the same power. Lastly, it permits great flexibility in terms of multi-banking, column decoding, multiple registering and porting and even allows pitch-matched logic functions for massively parallel processing. The architecture exploits the enhanced metal layer availability in mixed DRAM/logic process and the lack of standard-product constraints in embedded use.