A single-chip low power DSP/RISC CPU with 0.25 /spl mu/m CMOS technology

We developed a PDC system LSI chip, which is embedded with a 16 bit fixed point DSP and a 32 bit RISC CPU by utilizing the latest 0.25 /spl mu/m CMOS technology. The DSP part was designed specifically for the personal digital cellular (PDC) system, which makes it possible to perform Pitch Synchronous Innovation-Code Excited Linear Prediction (PSI-CELP) operations with 38 MIPS in one chip. Moreover, various techniques were applied to this device to achieve low power consumption; only 17 mA (0.34 mA/MIPS) at 1.8 V for a 50 MIPS operation on the DSP block.