Heterogeneous photonic Network-on-Chip with dynamic bandwidth allocation

Future multicore chips will have hundreds of heterogeneous components including processing engines, custom logic, GPU units, programmable fabrics and distributed memory. Such multicore chips are expected to run varied multiple parallel workloads simultaneously. Hence, different communicating cores will require different bandwidths leading to the necessity of a heterogeneous Network-on-Chip (NoC) architecture. Simply over-provisioning for performance will invariably result in loss of power efficiency. On the other hand, recent research has shown that photonic interconnects are capable of achieving high-bandwidth and energy-efficient on-chip data transfer. In this paper we propose a dynamic heterogeneous photonic NoC (d-HetPNOC) architecture with dynamic bandwidth allocation to achieve better performance and energy-efficiency compared to a homogeneous photonic NoC architecture with the same aggregate data bandwidth.