A 12-Bit 96Msample/s double-data-rate (DDR) pipeline ADC with speed and noise optimization for CMOS image sensors

In this paper, a 12-bit pipeline ADC with double-data-rate topology is proposed for high-speed CMOS image sensors (CIS). With a unique ping-pang architecture and a pseudo-noise cancellation scheme implemented, the designed ADC achieved a high sampling rate of 96Ms/s and with a good linearity and noise performance. The proposed ADC and image sensor chips are fabricated in the GSMC 0.13μm high-voltage mixed signal CMOS process. According to the simulation result, the SFDR performance is 77dB at 11.4375MHz input and DNL and INL are measured at -0.35LSB/+0.15LSB and -6LSB/+6LSB respectively. The area of the ADC is 1.85mm
²
. Powered with 3.3V power supply, the input range is ±1.8V and the power consumption of the ADC is 70mW.