Compact modeling of LDMOS working in the third quadrant

This paper presents a method to model the drain current of LDMOS working in the 3
^rd
quadrant (Vds<;0), which is important for power management IC design. The DIBL effect in 3
^rd
quadrant is shown to be much more significant than that in 1
^st
quadrant (Vds>0), and is not captured by the existing LDMOS models. Also, the threshold voltage model is not accurate in 3
^rd
quadrant, where the drain-body junction is forward biased. Consequently, the existing LDMOS models underestimate the 3
^rd
quadrant drain current in the sub-threshold region. A drain current expression taking into account these effects for the sub-threshold region is developed and added to the device model through a SPICE component bsource. The modeling accuracy of the drain current in the 3
^rd
quadrant is significantly improved.