A 32-Gb/s 9.3-mW CMOS equalizer with 0.73-V supply

A CTLE/DFE cascade incorporates inductor nesting to reduce chip area and latch feedforward to improve the loop speed. Realized in 45-nm CMOS technology, a 32-Gb/s prototype compensates for a channel loss of 18 dB at Nyquist while providing an eye opening of 0.44 UI at BER <; 10
^-12
.