Hysteresis cycle in the latch-up characteristic of wide CMOS structures

Experimental results are interpreted in terms of a simple lumped-element model that is also used to reproduce the hysteresis phenomenon with discrete components. The hysteresis is related to a three-dimensional (3-D) nonuniformity in the current distribution. Such hysteresis can lead to an erroneous evaluation of latchup parameters, such as the holding current density.<
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