Flash-based FPGAs in space, design guidelines and trade-off for critical applications

Availability of independent and dynamic radiation test results for Flash-based Field Programmable Gate Arrays paves the way to their utilization as alternative to established one-time-programmable antifuse-based solutions. Thanks to rad-hard-by-design (RHBD) techniques and specific validation procedures, those devices can be made at least as resilient with respect to Single Event Upsets (SEU) as the antifuse. This paper shows how the grade of reliability is dependant on the fault-tolerant techniques applied to the logic and the expected performances and design overheads of the logic itself. If correctly managed, the design overhead inferred by those techniques instead of becoming an additional development hurdle, may allow the exploit of the greater flexibility and performances of Flash FPGAs with respect to antifuse. The definition of the margins and trade-offs for use of RHBD techniques in space-borne Flash FPGAs as well as the Single Event Upsets mitigation techniques needed to be applied to the inner programmable logic will be presented.