Geometry Optimization of Planar Hall Devices Under Voltage Biasing

In this paper, a method is developed to optimize the geometry and to improve the sensitivity of four-terminal planar Hall devices under the voltage biasing. Using the conformal mapping, we can construct geometrically different Hall devices with the same sensitivity. The Hall voltage sensitivities thus obtained are close to the theoretical limit. Our analysis is verified by a recent experiment on graphene Hall devices, as well as previous theoretical works.