Compact hardware for real-time multi-line beamforming

Parallel beamforming is increasingly used, since it can deliver imaging frame rates (IFRs) higher than those achievable with standard approaches. In plane wave imaging, for example, IFRs of several kHz can be obtained. In a direct real-time implementation, each line is simultaneously processed by a corresponding hardware beamformer (BF), so that N-line parallel bemforming needs N hardware BFs. This makes the electronics complex and cumbersome, and only powerful GPUs or multiple FPGAs can achieve the required performance. In this work, a simple and compact architecture for real-time multi-line beamforming is proposed. A single BF implemented in FPGA efficiently works at the maximum frequency permitted by the device, so that several lines from the same channel-data are serially processed. The multi-line BF has been implemented in the ULA-OP research scanner and tested on B-Mode and Color-Mode applications.