An Area Efficient SEU-Tolerant Latch Design

This paper presents a new SEU-tolerant latch design based on Quatro and NMOS feedback transistors. By using these feedback transistors, the SEU susceptibility is decreased because of the cutoff feedback loop. Simulation results demonstrate that the proposed design is immune to static single node upsets. The proposed latch and the reference Quatro were designed and fabricated on a 130 nm process. The test chip was exposed to heavy ions at the TAMU Cyclotron facility. The testing results show that the proposed design has a higher upset LET threshold and lower cross-section when compared to the reference latch. Its lower SEU vulnerability comes with small area penalty.