Efficient charge recovery logic for power gating in logic circuits

This paper focuses on reducing the power, area and the gate counts. In this paper, Asynchronous Coarse Grain Power gated Logic (ACGPL) has been implemented. This design comprises both the advantage of Asynchronous circuits and adiabatic logic design. Each pipeline stage in the ACGPL consists of adiabatic logic gate and handshake controller. Adiabatic logic gate is used to perform the logic function of the stage and the handshake controller is used to communicate with the neighboring devices and provide power to logic gates. In the ACGPL circuit, logic gates obtain power and turn into active only when performing useful computations, and idle logic gates are not powered and thus have negligible leakage power dissipation. The Partial Charge Reuse (PCR) mechanism can also be integrated in this paper which is used to control the charge reuse between two stages. The work involves the comparison of Asynchronous Coarse Grain Power gated Logic (ACGPL) with the Asynchronous Adiabatic Power gated Logic (AAPL). The main drawback of fine grain power gating is adding a sleep transistor to every cell that is to be turned off imposes a large area penalty, and individually gating the power of every cluster of cells creates timing issue introduced by inter-cluster voltage variation that are difficult to resolve. Most power-gating designs prefer the “coarse-grain” sleep transistor implementation than the “fine-grain” implementation which incurs large area penalty and higher PVT sensitivity. The ACPL with PCR (ACGPL-PCR) is compared with the AAPL without PCR (AAPL w/o PCR). The ACGPL-PCR is 13% better than the AAPL w/o PCR.