An Experimental Approach to Accurate Alpha-SER Modeling and Optimization Through Design Parameters in 6T SRAM Cells for Deep-Nanometer CMOS

We report a detailed analysis about the memory soft error rate (SER) dependence with transistor design parameters for six-transistor (6T) SRAM cells fabricated on a 65-nm CMOS commercial technology. SER data are obtained from accelerated test with an Am-241 alpha source. Five 6T cells with different nMOS and pMOS transistors size combinations were fabricated and characterized. After verifying that transistor width increase always provides higher critical charge values, SER data show that this value is improved only when increasing the pMOS transistors width. Memory cells containing non-minimum-width nMOS transistors always exhibit worse SER values than cells with minimum-size ones. In addition, one cell with a higher Q
_crit
than another can show a worse SER depending on the transistor type whose size is being enlarged. Accordingly to this, we have found that SER may be increased by 76% without modifying cell structure nor impacting cell area. This behavior is qualitatively and quantitatively explained through an analytical model that relates SER to Q
_crit
and the transistor design parameters.