A high resolution transimpedance amplifier for use in a 10-bit 200 MS/s current mode SAR ADC

An approach towards a high speed current mode SAR ADC is presented. Even though SAR ADCs based on charge redistribution have been significantly improved in efficiency and operating frequency, they are still limited by the settling requirements of the switched capacitor DAC. To overcome this limitation, we propose the use of a current mode SAR ADC incorporating a current steering DAC operating at 2 GS/s and an overall Nyquist rate conversion speed of 200 MS/s. In this paper, the main focus is placed on the design of a high-resolution low-input-impedance transimpedance amplifier (TIA) used as the comparator preamplifier in the proposed current mode SAR ADC. The TIA converts the difference between the DAC feedback current and the output current of the input transconductance (Gm) stage to a voltage which is then quantized by a latch. For high-speed operation, trade-offs between input resistance, noise and voltage headroom pose challenges in the design of the high-speed TIA. More specifically, achieving a low input-referred noise current requires larger headrooms and thus higher supply voltages, which in turn reduces the TIA power efficiency. Thus, input impedance and input-referred noise current are the key determining factors for the design of high-speed TIAs in current based SAR ADCs. Our analysis is compared against a schematic level implementation in a 1.2 /1.8V 90nm CMOS technology. The TIA implementation is simulated on transistor level to achieve an overall resolution of 10 bit in the proposed current based SAR ADC together with the input Gm and current steering DAC over a Nyquist band from DC to 100 MHz.