Enhancing the input bandwidth of CMOS track and hold amplifiers

This paper presents a method to increase the input bandwidth of switched capacitor (SC) track and hold amplifiers (THAs), which is particularly suitable for time-interleaved analog-to-digital converters (ADCs). With a simple model for the track and hold stage, it is shown that frequency compensation techniques at the input of the THA can substantially increase the bandwidth at the controlled cost of increased distortion. A design example shows a bandwidth increase of 60% for a THA in a 4-bit ADC.