Process integration, improvements, and testing of Si interposers for embedded computing applications

A high performance embedded computing module was enabled and demonstrated with the implementation of a 3D Si interposer. The interposer contained front and backside multilevel metallization (MLM) with through-Si vias (TSVs) on 150mm wafers. The front-side MLM (5 levels) was fabricated with a dual damascene process. Four 2 um thick Cu routing layers with 2 um oxide dielectric layers and one pad layer were used in the front-side MLM. The TSVs were fabricated using a vias-last, unfilled via process. Due to improved process modules, contact chain test structures between the front-side MLM layers with 20,064 vias had electrical yields as high as 100%. Etching process conditions for the TSV process flow were also optimized to result in 100% yield on contact chains that contain up to 540 TSVs. These optimized etching conditions produced low TSV resistances (<;30 mΩ) and high TSV isolation resistance (>100MQ/via at 3.3V) for the embedded computing module (ECM). Two die from the 1
^st
generation interposer (3.97 cm × 3.67 cm die size) showed good continuity and isolation for 99% of the functional circuit path nets. A second generation design was recently fabricated that, through a combination of design changes and process optimizations, resulted in improved test capacitor performance, higher via chain yields, and increased power plane yields. Design changes were also implemented to enhance the high speed signal propagation properties of the TSVs. Specifically, the selection of 80 μm TSV diameters in 500 μm thick 100 Ω-cm substrates was made to improve the S
₁₁
and S
₂₁
properties of the TSVs over the frequency range of 1-4 GHz. Details of the design changes and process improvements implemented on the completed second generation ECM die and test die are discussed, along with test results from each type of die.