A 29ns 8Mb EPROM With Dual Reference-column ATD Sensing

A 29ns 8Mb EPROM in a submicron double-layer metal CMOS technology serves high-density applications dominated by 16b and 32b microprocessors and microcontrollers. The 8Mb CMOS EPROM technology uses 0.8μm lithography. The improvements in resolution, dimensional control and registration over the previous generation allow scaling the area of the floating-gate EPROM cell to 6.5μm2 .1 Peripheral circuit layout density is improved through the use of p-epi on a p+ substrate, which allows compact n+/p+ spacing with latchup immunity, and through the use of two full metallization layers in addition to a silicide layer for maximum density in the decoder and the logic areas. Improved circuit performance in the periphery is achieved through the use of scaled LDD n-channel and LDD pchannel transistors with electrical channel lengths of0.75μm and 0.7μm, respectively. In addition, the double-layer metal reduces circuit path lengths and associated RC delays. Table 1 summarizes the key technology attributes.