A Single-chip Digital PLL System For TV Image Processing

This single-chip all-digital phase-locked loop (PLL) system including voltage-controlled oscillator (VCO) and phase detector with no analog components receives 8b digital television image data sampled every 70ns and synchronizes it to the television horizontal sync (HSYNC) signal. The chip is applicable in TV image processing systems utilizing digital TV signal processing ICs.1,2 The circuit corresponds to a second-order perfect integral loop PLL with VCO frequency range of 14.31818MHz :t:10% and response time under 5 HSYNC cycles. The key to realization of the LSI was development of a digital phase detector and the adoption of the PLL architecture with interpolation filter shown in Figure 1. Prior digital television image processing systems generate data synchronous to the HSYNC signal by changing the frequency of the sampling clock with the analog PLL. An analog VCO is used to make frequency changes in the sampling clock and cause the phase of the data sampled by the analog-to-digital converter to shift and synchronize with the HSYNC signal. This system realizes the same function, but instead of changing the frequency of the sampling clock, causes the phase of the sampled digital data to shift by changing the phase characteristics of the interpolation filter through which the data propagates. This filter can be realized digitally and renders the analog VCO used in ordinary PLL unnecessary. Filter characteristics are controlled by a digital "VCO" which generates phase correction data so that incoming data is phase corrected to match the data which would have been sampled by an analog VCO-generated sampling clock. Thus the incoming image data can be phase corrected without need of an actual analog VCO with attendant characteristics degradation due to analog factors such as aging, temperature dependence, digital noise from digital parts of the system.