MBiCMOS: A Device And Circuit Technique Scalable To The Sub-micron, Sub-211 Regime

The delay advantage of conventional BiCMOS over CMOS is lost at reduced supply voltage due to faster delay degradation. Complementary BiCMOS and level-shifted BiCMOS have been suggested as possible solutions but suffer either from increased process complexity (pnp devices) or circuit complexity (extra devices per gate). This paper describes a merged BiCMOS (MBiCMOS) gate that is scalable to the sub-micron, sub-2V regime. The gate is fabricated in a 1μm conventional BiCMOS technology with triple-diffused BJTs. The cross-over voltage in the delay vs. supply curve at which the delay becomes greater than CMOS is reduced from 3V for 1μm BiCMOS to 2.4V for 1μm MBiCMOS and from 3.2V to 2.6V in the 2μm technology. Circuit simulation using measured device parameters in a 0.5μm technology shows that the crossover occurs below 2V. The gate uses merged pMOS-npn devices that require no additional process steps. Compared to conventional BICMOS, the MBiCMOS gate uses 4 instead of 6 discrete devices, occupies 35% less area and shows no increase in power-delay product.