0.5/spl mu/m 2M-transistor BipnMOS Channelless Gate Array

This channelless gate array uses 0.5µm BiCMOS technology integrating more than 2 million transistors on a 14x14.4mm chip. The BipnMOS cell is used to achieve 230ps logic gates with large margins. High-speed and high-density BiCMOS macro cells including RAM, ROM and CAM are also included. To ensure high reliability of the 0.5µm gate-length