A 45ns 64Mb DRAM With A Merged Match-line Test Architecture

This single 3.3V 64Mb DRAM uses currently-available 0.4μm CMOS photolithography (i-line). In this RAM, merged match­ line test (MMT) data-line architecture provides both faster access time and shorter test time, with minimum chip area penalty. Using a parallel MMT technique, which is an exten­sion of MMT, a 64kb parallel test is executed.