7ns 4Mb BICMOS SRAM With Parallel Testing Circuit

This 7ns 4Mb ECL SRAM uses a wired-or data bus in the sense circuit, a column-redundant circuit and a 16b parallel testing circuit. The RAM is fabricated using a double-metal and triple-polysilicon 0.6μm oxide-surrounded bipolar and a CMOS (0-BiC) process. J/0 levels are ECL lOK compatible.