Novel square root algorithm and its FPGA implementation

Square root is a basic arithmetic operation which is used in digital signal processing. Due to complex algorithm it is difficult to implement on FPGA. This paper presents a novel square root algorithm which is based on some ancient Indian mathematics (Vedic mathematics) formula called Dwandwa Yoga. The proposed algorithm uses lowest area. In this paper we are using 24-bit (16bit+8bit) floating point input and 16-bit (8bit+8bit) floating point output. We will discuss the proposed square root algorithm, its hardware description, and its FPGA implementation using Xilinx tool. The cost for this algorithm on the SPARTAN-3E XC3S500E is 173 LUTs (4 input), 90 slices, 99 slice flip flops. The design consumes 90.9 mW power and can be operated at frequency 68.22MHz. This algorithm uses only adders, subtractors and registers which leads to consume less area, less power and high operating frequencies. The proposed algorithm can be implemented on decimal numbers.