Verification of non-mainline functions in todays processor chips

In a modern chip development cycle non-mainline / non-functional verification is gaining importance compared to traditional functional verification tasks and takes up to one third of the total verification effort. The purpose of non-mainline logic is to operate, maintain, and debug the chip. Ever-increasing complexity of the chip, thus, directly affects the complexity of the non-mainline logic and as a result, the verification thereof. Moreover, the non-mainline world is no longer pure hardware, but an intricate mix of software and hardware. We claim that traditional constrained-random verification methods are not valid for the non-mainline domain and the verification should be based on usage scenarios. Moreover, these scenarios must be formally specified to avoid ambiguity and allow collaboration of different teams involved in the chip development.