Design and analysis of Racetrack memory based on magnetic domain wall motion in nanowires

Current induced domain walls (DW) motion in magnetic nanowires or nano-stripes presents a novel approach to store and convey data. Combining with magnetic tunnel junction (MTJ) nanopillars, Racetrack memory (RM) becomes a new class of non-volatile memory thanks to its large storage capacity and fast data access. However, we need a relatively high current passing through the nanowire to move magnetic domain walls. This leads to a big challenge to design integration circuits and architecture for RM beyond the device level research. For instance, we find that the resistivity of nanowire material is a very critical parameter for the RM design. In this paper, we present the design of racetrack memory taking into account the physical prospects of magnetic domain wall motion in nanowires. By using an industrial CMOS 40 nm design kit and a perpendicular magnetic anisotropy (PMA) RM compact model, mixed SPICE simulations have been performed to analyze the area (e.g. 1 F2), speed and reliability performances.