Overestimation of Short-Channel Effects Due to Intergate Coupling in Advanced FD-SOI MOSFETs

The short-channel effects (SCE) in advanced fully depleted silicon-on-insulator MOSFETs are investigated by showing the importance of the intergate coupling. Experimental results highlight that part of the SCE is due to the contribution of the opposite-gate, leading to systematic overestimation of the threshold voltage roll-off and drain-induced barrier lowering (DIBL) effects. Numerical simulations confirm that the impact of back-gate SCE depends on the device structure (film and oxide thickness) and bias. A basic model is presented, which enables the identification of the genuine SCE at each gate. To mitigate or fully cancel the threshold voltage roll-off and DIBL, we propose simple and pragmatic back-biasing schemes.