Experiments on two clock countermeasures against power analysis attacks

Two countermeasures against DPA/CPA attacks have been designed, tested and compared on an AES encoding coprocessor implemented on FPGA. Both countermeasures are based on altering the clock signal and can be readily implemented at RTL design stage. Experimental results based on first order CPA attacks confirmed the effectiveness of both the countermeasures in protecting the SBOX output, showing that even with the acquisition of 300000 power curves, the encryption key can't be revealed by the relevant correlation peaks.