Noise modeling of source inductive degeneration low noise amplifier in 0.18-µm CMOS technology

This paper presents a mathematical modeling of noise performance in source inductive degeneration topology which widely used in narrow band amplifier. The proposed model is conducted by utilizing a small-signal MOSFET model to generate the effective transconductance of circuits. The performance of noise figure can be preserved by selecting the device width while preserving a stable bias voltages and maintaining the device length unchanged. Using the mathematical model, a low noise amplifier is designed and obtain the noise figure of 2.5-dB, an remarkable figure of merit among reported LNAs in 0.18-μm CMOS technology.