Lower bounds of the size of Shared Structurally Synthesized BDDs

A novel type of BDDs called Shared Structurally Synthesized BDDs (S3BDD) is presented as an extension of the SSBDDs, and a method is given to minimize the size of the model. As in case of SSBDDs, the S3BDDs have linear complexity compared to the size of the logic circuit they represent, and they are characterized by the property of one-to-one mapping between the nodes of graphs and signal paths in the circuit. Minimization of S3BDDs makes it possible to get higher rates in fault collapsing, and to speed-up logic simulation as a main tool in delay analysis, fault reasoning and test generation. A lower bound is developed for the size of S3BDDs to evaluate the results of S3BDD synthesis, and it is shown that this bound can be reached rather closely by a straightforward method. Experimental results demonstrate that the S3BDDs represent the most compact BDD based model representing the structure of the digital circuits, which has in average 1.5 times less nodes than the SSBDDs.