A design of an area-efficient 10-GHz phase-locked loop for source-synchronous, multi-channel links in 90-nm CMOS technology

This paper presents a design of an area-efficient 10-GHz PLL for source-synchronous, multi-channel applications. To be applied in the multi-channel application, the proposed PLL is implemented without use of any high-cost inductor to minimize silicon area while achieving 10-GHz operation frequency. A modified CML type ring-VCO is used to make the VCO outputs have consistent signal amplitude. The proposed PLL is fabricated in 90-nm low-power CMOS technology. The prototype IC occupies 0.075mm
²
of active area and dissipates 87.6-mW power from 1.2-V supply including a 10-GHz clock driver.