Performance modeling of virtualized custom logic computations

Virtualization of custom logic computations (i.e, by sharing a fixed function across distinct data streams) provides a means of computing multiple streams using shared hardware resources. The hardware can be context-switched to support virtualization using C-slow techniques (fine-grained context-switching) or by adding a secondary memory (coarse-grained context-switching). The performance of these computations depends on the circuit, technology, number of pipeline stages, number of streams, cost of a context switch, scheduling period, and arrival rate. In this paper, we analyze a virtualized hardware design and develop a set of analytic modeling equations for predicting the performance of these circuits. We then validate the model equations using a discrete-event simulation.