A Fast Technique to Screen Carrier Generation Lifetime Using DLTS on MOS Capacitors

We have developed a technique for fast screening of carrier generation lifetime in ultraclean silicon wafers by employing deep-level transient spectroscopy (DLTS) measurements on metal–oxide–semiconductor-capacitor (MOS-C) test structures. Results show that the screened lifetime is of sufficient accuracy to distinguish metallic impurities with densities as low as
\(10^{10}\)
cm
\(^{-3}\)
in thin p/p
⁺
silicon epitaxial layers. The widely used classic pulsed MOS-C technique is shown to be inaccurate and unable to separate bulk and surface components of the lifetime, while its modified and more accurate versions are time consuming and unaffordable for process screening purposes.