A 65 nm single stage 28 fJ/cycle 0.12 to 1.2V level-shifter

A conventional level-shifter is modified to extend the operation range down to subthreshold regime. Leakage current is reduced by utilizing transistor stacking, channel stretching, and reverse body biasing. The design has a standard-cell compliant layout and is fully integrated in a conventional digital design flow. The level-shifter is manufactured in 65nm CMOS, and functionality is verified by measurements. The proposed design is capable of converting 0.12 to 1.2V in a single stage, and has a static power consumption of 640pW at a 0.12 to 1V conversion. The minimum energy/cycle of 28 fJ/cycle with a conversion speed of 72MHz was observed at 0.3 to 1V conversion.