Effect of Source/Drain Lateral Straggle on Distortion and Intrinsic Performance of Asymmetric Underlap DG-MOSFETs

This paper presents a systematic study of the effect of source/drain (S/D) implant lateral straggle on the RF performance of the symmetric and asymmetric underlap double gate (UDG) MOSFET devices. The length of the underlap regions (L
_un
) on each side of the gate is a critical technology parameter in determining the performance of UDG-MOSFETs. However, the value of L
_un
is susceptible to variation due to S/D implant lateral diffusion. Therefore, it is critical to investigate the impact of S/D implant lateral straggle on the performance of UDG-MOSFETs. This paper shows that the improvement in the RF performance of the UDG-MOSFETs over the conventional DG-MOSFETs can be achieved by optimizing the S/D lateral straggle of the asymmetric UDG-MOSFETs. The RF performance study includes intrinsic capacitances and resistances, transport delay, inductance, and the cut-off frequency.