LatEst: Latency estimation and high speed evaluation for wormhole switched Networks-on-Chip

In this paper a new latency analysis method for wormhole switched Networks-on-Chip is presented. This method can be used for many wormhole switched NoC with flit interleaving and static routing. The latency estimator is intended to be used for a fast performance estimation and evaluation processes where a simulation is too computationally intense. This could especially be used for optimization problems to achieve a fast evaluation process. To gain high speed, an abstract model is designed where absolute cycle accuracy is omitted. To model latency, the estimator uses an approach where packets are seen as data streams through the network, allocating a path with a certain sending rate depending on competition with other packets.