Study on ESD protection design with stacked low-voltage devices for high-voltage applications

ESD protection with stacked low-voltage (LV) devices are proposed to form an area-efficient design for high-voltage (HV) applications in a 0.25-µm HV BCD process. By using the stacked configuration, the LV devices can provide scalable triggering voltage (V
t1
) and holding voltage (V
h
) for various HV applications. Experimental results in silicon chip have verified that the stacked LV devices can exhibit a higher ESD robustness per unit layout area as comparing to the ESD clamp circuit with HV device.