Effects of sidewall scallops on open tungsten TSVs

In order to examine the effects of sidewall scallops on through-silicon via (TSV) performance, the etch processes required to generate several TSV geometries are simulated and the resulting structures are imported into a finite element tool for electrical parameter extraction and reliability analysis. The electrical models, which were confirmed using experimental measurements with non-scalloped structures, are applied to the simulated TSV devices. The effects of the scalloped features are investigated by comparing the performance of a TSV with scalloped sidewalls to one with flat walls. In addition, the variation in TSV performance, when the sidewall scallop height is varied, is analyzed. A link between increased scallop height and increased resistance and signal loss is observed. The maximum thermo-mechanical stress in the structure is also noted to increase with the presence of large scallops, but the overall average stress does not vary significantly.