New insights about oxide breakdown occurrence at circuit level

With device scaling, electric fields across the gate oxide have increased and supply voltages have been reduced not as much as the gate-oxide thickness, intensifying the probability of dielectric breakdown events for transistors. In this context, the more the oxide thickness is reduced, the more the oxide breakdown degradation is progressive. However, the first breakdown event does not always cause a functional failure in digital circuits. As a consequence, relaxation of the predicted lifetime could be accounted at circuit level with respect to the area scaling. First, this paper deals with characterization of soft breakdown events at device level. Post-breakdown degraded parameters and their dispersion are identified and quantified. Then a transistor-level model of breakdown is presented; it handles distributions of Time to Breakdown, breakdown spots localization and parameters degradation (ΔV
t
, evolution of I
d
/I
s
, ΔI
g
, ΔI
dlin
…). This model is implemented in API, it takes into account both BTI and oxide breakdown degradation contributions and is calibrated for a range of breakdown severity used at circuit level. A custom digital circuit has been implemented to measure the impact of multiple oxide breakdowns on static current and oscillation frequency. The theoretical models of multiple oxide breakdown events reproduce properly the experimental behavior. Finally the case of hard breakdown events in a data path is investigated and the impact on percentage errors is discussed.