A new method for extracting interface state and border trap densities in high-k/III-V MOSFETs

Increased CMOS performance requires the introduction of alternative materials as substrate and gate dielectrics. III-V materials and in particular InGaAs can provide superior electron mobility compared to classic Si substrates. However, such substrate materials have non-optimal dielectric-semiconductor interfaces that can drastically reduce the device performance. Techniques for the extraction of interface and border trap profiles are required for the characterization and optimization of these materials. In this paper we present a new procedure relying on a physical charge-transport model including trap assisted tunneling, lattice relaxation and trap assisted generation and recombination of minority carriers. The procedure allows the extraction of interface and border trap densities from capacitance voltage characteristics measured at different frequencies. The technique is applied to characterize InGaAs MOSFETs Al
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stacks of different thicknesses and fabricated with different annealing conditions.