A quad-channel 112–128 Gb/s coherent transmitter in 40 nm CMOS

A quad-channel, 112–128 Gb/s coherent DP-QPSK transmitter in 40 nm CMOS is presented. The 27.9–32.1 Gb/s TX features a half-rate architecture with a 2-tap FIR. The measured output has an amplitude of 1.2V
pp-diff
with 1.3 ps deterministic jitter (DJ). The DP-QPSK TX's precoded data alignment is maintained through the quad-lane transmitter by the use of an automatic synchronous feedback loop, removing the need for a master global reset. The PLL outputs the full-rate and half-rate clock with ±0.5 UI skew adjustment relative to the data. The power consumption of the transmitter and PLL is 712 mW.