A low temperature 12 ns DRAM

Results are presented of measurements on cryogenic operation of a high-speed 512-kb CMOS dynamic RAM (DRAM). Comprehensive investigations focused on circuit concerns particularly relevant to high speed. The measured access time was 12 ns, and the results show that noise, power, and soft error rate do not preclude very-high-speed DRAM operation at cryogenic temperatures. Compared to room-temperature operation the observed improvement in access time was about 1.7* for V/sub DD/=5 V. Compared to 85 degrees C operation the improvement was 2.2*.<
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